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Npaj-txheej txheem ntawm cov rooj vag uas muaj vaj huam sib luag

Npaj-txheej txheem ntawm cov rooj vag uas muaj vaj huam sib luag

Mar 11, 2019

Logic blocks

Yooj yim piv txwv ntawm ib lub xov tooj ntawm logic (LUT - Saib lub rooj, FA - Full adder, DFF - D-type flip-flop)

Qhov FPGA architecture feem ntau muaj ib qho ntawm cov logic blocks, [note 1] I / O tas nrho, thiab kev mus raws kev. Feem ntau, tag nrho cov kev raws hauv kev muaj qhov dav dav (xov tooj ntawm xov hlau). Ntau cov I / O tag nrho yuav haum rau hauv qhov siab ntawm ib leej los yog lub dav ntawm ib sab hauv cov array.


Ib daim ntawv thov kev sib tw yuav tsum tau muab sib npaug rau hauv FPGA nrog cov kev pab tsim nyog. Thaum tus naj npawb ntawm CLBs / LABs thiab I / Os yuav tsum tau txiav txim siab tau yooj yim los ntawm qhov tsim, tus naj npawb ntawm cov kev xav tau yuav txawv ib qho txawm tias cov qauv tsim muaj cov logic tib yam.


Piv txwv li, txoj kev hloov khawm crossbar yuav tsum muaj ntau txoj kev tshaj li ib txoj kab ke systolic nrog tib qhov rooj suav. Vim tias tsis siv cov kev khiav haujlwm tsis zoo (thiab txo qhov kev ua tau zoo) ntawm qhov tsis tau muab kev pab cuam, cov FPGA cov lag luam sim muab cov kev txaus siab txaus kom ntau cov qauv tsim nyog ntawm cov lus xaiv cov ntxhuav (LUTs) thiab I / Os yuav ua tau routed. Qhov no yog txiav txim tau los ntawm cov kev kwv yees xws li cov uas tau los ntawm tus nqi xauj tsev lossis los ntawm cov kev sim uas muaj cov qauv tsim tawm. Raws li ntawm 2018, network-on-nti architectures rau routing thiab interconnection yog tsim.


Feem ntau, ib qho logic thaiv muaj ob peb lub hlwb cov ntsiab lus (hu ua ALM, LE, hlais thiab lwm yam). Ib lub xov tooj ntawm tes muaj 4-lute [timeframe?], Ib qho kev sib tw (FA) thiab D-type flip-flop, raws li tau hais los saum no. Cov LUTs yog nyob rau hauv daim duab no cais ua ob 3 tawm tswv yim LUTs. Hauv hom qee cov neeg koom ua ke hauv lub 4-lute LUT los ntawm cov laug multiplexer (mux). Hauv hom ntawv xam pom, lawv cov khoom siv tau pub rau tus adder. Kev xaiv hom yog programmed rau hauv nruab nrab MUX. Cov zis yuav ua tau xws li synchronous los yog asynchronous, nyob ntawm lub programming ntawm mux rau sab xis, hauv daim duab piv txwv. Hauv kev xyaum, tag nrho lossis ib ntu ntawm cov adder muab cia ua lub zog rau hauv LUTs thiaj li txuag tau qhov chaw.


Nyuaj cov blocks

Niaj hnub nimno FPGA cov tsev neeg nthuav tawm raws li cov peev txheej saum toj no kom muaj kev ua haujlwm siab dua nyob rau hauv silicon. Muaj cov kev ua haujlwm tshaj plaws nyob rau hauv Circuit Court thiaj li tsim nyog rau qhov chaw thiab yuav muab cov zog no nce siab dua piv rau lawv los ntawm cov txheej xwm thawj. Piv txwv ntawm cov no muaj xws li multipliers, generic DSP blocks, embedded processors, kub ceev I / O logic thiab nco nco.


Cov Higher-End FPGAs muaj peev xwm muaj kev kub ceev multi-gigabit transceivers thiab nyuaj IP cores xws li processor cores, Ethernet nruab nrab qhov chaw tswj kev tswj hwm, PCI / PCI Express controllers, thiab lwm tus sab nrauv controllers. Cov cores no muaj nyob rau ntawm cov cuab yeej tawm suab paj nruag, tab sis lawv ua tau tawm ntawm transistors es tsis txhob LUTs ces lawv muaj ASIC theem kev ua tau zoo thiab lub zog noj tsis tau noj ib qho tseem ceeb ntawm cov ntaub ntawv siv ntaub, tawm hauv cov ntaub ntawv dawb rau daim ntawv thov tshwj xeeb logic. Cov multi-gigabit transceivers tseem muaj cov kev ua haujlwm siab tshaj analog thiab cov khoom siv sib txuas nrog cov high-speed serializers thiab deserializers, yam uas tsis tuaj yeem ua tawm ntawm LUTs. Cov txheej txheem ntau dua PHY [txhais tau tias] txheej functionality xws li kab coding tej zaum yuav ua tau los sis tsis ua raws nraim li cov neeg tawm tsam thiab cov neeg tsim kev lag luam hauv cov qauv nyuaj, nyob ntawm FPGA.


Clocking

Feem ntau ntawm Circuitry tau txua hauv FPGA yog qhov sib txuas ua haujlwm uas yuav tsum muaj lub teeb liab. FPGAs muaj kev sib txuas lus thoob ntiajteb thiab lub cheeb tsam kev sib koom tes rau lub sijhawm thiab rov qab xaiv dua kom lawv tuaj yeem nqa nrog tsawg tshaj plaws. Tsis tas li ntawd, FPGAs feem ntau muaj cov analog raug xauv voj thiab / lossis kaw qeeb qeeb dua lub vev xaib kom coj los ua dua tshiab moos frequencies nrog rau cov khoom xyaw. Cov qauv tsim muaj peev xwm siv tau ntau lub ntoos nrog ntau zaus thiab theem kev sib raug zoo, txhua qhov kev cais cais cov puav. Cov xovtooj moos no tuaj yeem tsim tawm los ntawm lub oscillator lossis lawv tuaj yeem tau rov qab los ntawm cov ntaub ntawv ceev ceev. Kev kho mob yuav tsum tau txais thaum tsim kom muaj lub voj voog khiav ntawm txoj kab sib chaws kom tsis txhob muaj kev tiv thaiv. FPGAs feem ntau muaj kev thaiv cov kab nrig uas muaj peev xwm ntawm kev ua haujlwm li dual chaw nres nkoj RAMs nrog cov sij hawm sib txawv, pab nyob rau hauv kev tsim kho ntawm lub tsev FIFOs thiab dual chaw nres nkoj uas txuas nrog kev sib txawv ntawm cov moos.


3D architectures

Kom ntsuag qhov loj thiab hwj huam tau siv ntawm FPGAs, cov neeg muag khoom xws li Tabula thiab Xilinx tau pib 3D los yog cov qauv kev teeb tsa. Tom qab qhia txog nws cov 28 nm 7-series FPGAs, Xilinx tau hais tias ntau qhov chaw siab tshaj plaws hauv cov FPGA cov khoom yuav raug tsim los siv ntau yam kev tuag nyob hauv ib lub pob, ntiav cov tshuab tsim rau kev tsim kho 3D thiab kev sib tsoo tuag.


Xilinx lub hom phiaj sib txuam ob peb (peb lossis plaub) lub cev FPGA tuag ib sab ntawm ib qho kev sib txuas ntawm silicon - ib qho ntawm silicon uas yog passive interconnect. Kev siv ntau qhov kev tua kuj tseem tso cai rau ntau qhov chaw ntawm FPGA kom tsim muaj cov txheej txheem sib txawv, raws li tus txheej txheem yuav tsum sib txawv ntawm FPGA ntaub nws tus kheej thiab kev kub ceev 28 Gbit / s serial transceivers. Tus FPGA tau ua nyob rau hauv txoj kev no yog hu ua FPGA heterogeneous.


Altera tus heterogeneous mus kom ze yuav siv ib qho monolithic FPGA tuag taus thiab txuas lwm tus tuag / yees mus rau FPGA siv Intel lub nruab inter-chunk interconnect choj (EMIB) technology.