Tsev > Exhibition > Ntsiab lus

Cov tswv yim microarchitectural Cov kev qhia xaiv

Mar 09, 2019

Kev qhia ntawv tau hloov mus rau ntau lub xyoo, los ntawm keeb kwm yooj yim heev rau tej zaum nyuaj (nyob rau hauv ntau yam). Nyob rau hauv xyoo tas los, load-store architectures, VLIW thiab EPIC hom tau nyob rau hauv xom lees. Architectures uas tabtom ua haujlwm nrog cov ntaub ntawv qhia muaj xws li SIMD thiab Vectors. Qee cov ntawv siv los qhia cov chav kawm ntawm CPU architectures tsis yog tshwj xeeb tshaj tawm, tshwj xeeb yog li ntawv CISC; ntau cov qauv tsim ntawm qhov qub dhau ntawm "CISC" yog qhov tseeb yooj yim dua li cov RISC cov niaj hnub ua tam sim no (ob peb lub hauv paus).


Txawm li cas los xij, qhov kev xaiv ntawm cov qauv siv los tsim kev lag luam yuav muaj kev cuam tshuam rau qhov nyuaj ntawm kev siv cov cuab yeej ua tau zoo. Lub tswv yim tseem ceeb, siv los tsim thawj cov RISC processors, yog los simplify cov lus qhia kom muaj tsawg kawg nkaus ntawm ib qho kev sib txawv ntawm cov ntsiab lus nrog ib qho kev sib txuas lus zoo thiab kev yooj yim. Xws li cov lus qhia zoo tau yooj yim fetched, decoded thiab tseg nyob rau hauv ib tug pipelined fashion thiab ib tug yoo zoo los txo cov zauv ntawm cov ntsiab lus logic kom ncav cuag kev khiav hauj lwm frequencies; Kev qhia cache-nco tau them rau kev khiav hauj lwm siab zog thiab qhov tsis sib haum raws li cov cai thaum lub sij hawm loj sau npe raug siv los ua qhov tseem ceeb ntawm cov cim xeeb (qeeb) ntau li ntau tau.