Tsev > Xov xwm > Ntsiab lus

FTDI qhov chaw FT_Gpu_Hal.c

May 08, 2019

#include "FT_Platform.h"


/ * API los initialize lub SPI interface * /

ft_bool_t Ft_Gpu_Hal_Init (Ft_Gpu_HalInit_t * halinit)

{

#ifdef ARDUINO_PLATFORM_SPI

pinMode (FT_ARDUINO_PRO_SPI_CS, OUTPUT);

pinMode (FT800_PD_N, OUTPUT);

digitalWrite (FT_ARDUINO_PRO_SPI_CS, HIGH);

digitalWrite (FT800_PD_N, HIGH);

#endif


#ifdef MSVC_PLATFORM_SPI

/ * Initialize cov libmpsse * /

Init_libMPSSE ();

SPI_GetNumChannels (& halinit-> TotalChannelNum);

/ * Los ntawm vim kuv kuv piv txwv tias tsuas yog ib qho mpsse cable txuas nrog PC thiab channel 0 ntawm lub mpsse cable siv rau cov kev lag luam * /

yog hais tias (halinit-> TotalChannelNum> 0)

{

FT_DEVICE_LIST_INFO_NODE devList;

SPI_GetChannelInfo (0, & devList);

printf ("Cov ntaub ntawv ntawm cov xov tooj channel% d:", 0);

/ * sau cov dev info * /

printf ("Txheeb = 0x% x", devList.Flags);

printf ("hom = 0 x% x", devList.Type);

printf ("ID = 0x% x", devList.ID);

printf ("LocId = 0x% x", devList.LocId);

printf ("SerialNumber =% s", devList.SerialNumber);

printf ("Nqe lus =% s", devList.Description);

printf ("ftHandle = 0x% x", devList.ftHandle); / * yog 0 tshwj tsis yog qhib * /

}

#endif

rov qab TRUE;

}


ft_bool_t Ft_Gpu_Hal_Open (Ft_Gpu_Hal_Context_t * party)

{

#ifdef MSVC_FT800EMU

Ft_GpuEmu_SPII2C_begin ();

#endif

#ifdef ARDUINO_PLATFORM_SPI

SPI.begin ();

SPI.setClockDivider (SPI_CLOCK_DIV2);

SPI.setBitOrder (MSBFIRST);

SPI.setDataMode (SPI_MODE0);

#endif

#ifdef MSVC_PLATFORM_SPI

ChannelConfig channelConf; // channel configuration

FT_STATUS txheej xwm;

/ * configure lub spi settings * /

channelConf.ClockRate = host-> hal_config.spi_clockrate_khz * 1000;

channelConf.LatencyTimer = 2;

channelConf.configOptions = SPI_CONFIG_OPTION_MODE0 | SPI_CONFIG_OPTION_CS_DBUS3 | SPI_CONFIG_OPTION_CS_ACTIVELOW;

channelConf.Pin = 0x00000000; / * FinalVal-FinalDir-InitVal-InitDir (rau dir 0 = hauv, 1 = tawm) * /


/ * Qhib tus thawj muaj channel * /

SPI_OpenChannel (host-> hal_config.channel_no, (FT_HANDLE *) & host-> hal_handle);

txheej xwm = SPI_InitChannel ((FT_HANDLE) party-> hal_handle, & channelConf);

printf ("handle = 0x% x status = 0x% x", host-> hal_handle, txheej xwm);

#endif

host-> ft_cmd_fifo_wp = host-> ft_dl_buff_wp = 0;

host-> status = FT_GPU_HAL_OPENED;

rov qab TRUE;

}


ft_void_t Ft_Gpu_Hal_Close (Ft_Gpu_Hal_Context_t * party)

{

host-> txheej xwm = FT_GPU_HAL_CLOSED;

#ifdef MSVC_PLATFORM_SPI

/ * Kaw cov channel * /

SPI_CloseChannel (host-> hal_handle);

#endif

#ifdef ARDUINO_PLATFORM_SPI

SPI.end ();

#endif

#ifdef MSVC_FT800EMU

Ft_GpuEmu_SPII2C_end ();

#endif

}


ft_void_t Ft_Gpu_Hal_DeInit ()

{

#ifdef MSVC_PLATFORM_SPI

// Tawm hauv MPSSE Lib

Cleanup_libMPSSE ();

#endif

}


/ * Cov APIs rau kev nyeem ntawv / kev sau ntaub ntawv tsis tu ncua tsuas yog siv me me xwb * /

ft_void_t Ft_Gpu_Hal_StartTransfer (Ft_Gpu_Hal_Context_t * host, FT_GPU_TRANSFERDIR_T rw, ft_uint32_t addr)

{

yog tias (FT_GPU_READ == rw) {

#ifdef MSVC_PLATFORM_SPI

ft_uint8_t Transfer_Array [4];

ft_uint32_t DimTransfered;


/ * Ua zoo nyeem cov ntawv nyeem * /

Transfer_Array [0] = addr >> 16;

Transfer_Array [1] = addr >> 8;

Transfer_Array [2] = addr;


Transfer_Array [3] = 0; // Dummy Readte

SPI_Write ((FT_HANDLE) host-> hal_handle, Transfer_Array, sizeof (Transfer_Array), & SizeTransfered, SPI_TRANSFER_OPTIONS_SIZE_IN_BYTES | SPI_TRANSFER_OPTIONS_CHIPSELECT_ENABLE);

#endif

#ifdef ARDUINO_PLATFORM_SPI

digitalWrite (FT_ARDUINO_PRO_SPI_CS, LOW);

SPI.transfer (ntxiv rau >> 16);

SPI.transfer (highByte (addr));

SPI.transfer (lowByte (addr));


SPI.transfer (0); // Dummy Readte

#endif

#ifdef MSVC_FT800EMU

Ft_GpuEmu_SPII2C_StartRead (addr);

#endif

host-> status = FT_GPU_HAL_READING;

} lwm {

#ifdef MSVC_PLATFORM_SPI

ft_uint8_t Transfer_Array [3];

ft_uint32_t DimTransfered;


/ * Ua zoo nyeem cov ntawv nyeem * /

Transfer_Array [0] = (0x80 | (addr >> 16));

Transfer_Array [1] = addr >> 8;

Transfer_Array [2] = addr;

SPI_Write ((FT_HANDLE) host-> hal_handle, Transfer_Array, 3, thiab SizeTransfered, SPI_TRANSFER_OPTIONS_SIZE_IN_BYTES | SPI_TRANSFER_OPTIONS_CHIPSELECT_ENABLE);

#endif

#ifdef ARDUINO_PLATFORM_SPI

digitalWrite (FT_ARDUINO_PRO_SPI_CS, LOW);

SPI.transfer (0x80 | (ntxiv rau >> 16));

SPI.transfer (highByte (addr));

SPI.transfer (lowByte (addr));

#endif

#ifdef MSVC_FT800EMU

Ft_GpuEmu_SPII2C_StartWrite (addr);

#endif

host-> status = FT_GPU_HAL_WRITING;

}

}


/ * Lub APIs rau kev sau ntaub ntawv tsuas hloov tau * /

ft_void_t Ft_Gpu_Hal_StartCmdTransfer (Ft_Gpu_Hal_Context_t * host, FT_GPU_TRANSFERDIR_T rw, ft_uint16_t suav)

{

Ft_Gpu_Hal_StartTransfer (party, rw, host-> ft_cmd_fifo_wp + RAM_CMD);

}

ft_uint8_t Ft_Gpu_Hal_TransferString (Ft_Gpu_Hal_Context_t * party, const ft_char8_t * hlua)

{

ft_uint16_t ntev = strlen (txoj hlua);

thaum (ntev -) {

Ft_Gpu_Hal_Transfer8 (party, * hlua);

hlua ++;

}

/ / Ntxiv ib daim thov raws li qhov xaus chij

Ft_Gpu_Hal_Transfer8 (party, 0);

}


ft_uint8_t Ft_Gpu_Hal_Transfer8 (Ft_Gpu_Hal_Context_t * host, ft_uint8_t tus nqi)

{

#ifdef ARDUINO_PLATFORM_SPI

rov qab SPI.transfer (tus nqi);

#endif

#ifdef MSVC_PLATFORM_SPI

ft_uint32_t DimTransfered;

yog hais tias (host-> txheej xwm == FT_GPU_HAL_WRITING) {

SPI_Write (host-> hal_handle, & value, sizeof (tus nqi), & SizeTransfered, SPI_TRANSFER_OPTIONS_SIZE_IN_BYTES);

} lwm {

SPI_Read (host-> hal_handle, & value, sizeof (tus nqi), & SizeTransfered, SPI_TRANSFER_OPTIONS_SIZE_IN_BYTES);

}


yog tias (SizeTransfered! = sizeof (tus nqi))

host-> status = FT_GPU_HAL_STATUS_ERROR;

rov qab tus nqi;

#endif

#ifdef MSVC_FT800EMU

xa Ft_GpuEmu_SPII2C_transfer (tus nqi);

#endif

}


ft_uint16_t Ft_Gpu_Hal_Transfer16 (Ft_Gpu_Hal_Context_t * host, ft_uint16_t tus nqi)

{

ft_uint16_t retVal = 0;

yog hais tias (host-> txheej xwm == FT_GPU_HAL_WRITING) {

Ft_Gpu_Hal_Transfer8 (host, value & 0xFF); // LSB ua ntej

Ft_Gpu_Hal_Transfer8 (host, (value >> 8) & 0xFF);

} lwm {

retVal = Ft_Gpu_Hal_Transfer8 (party, 0);

retVal | = (ft_uint16_t) Ft_Gpu_Hal_Transfer8 (host, 0) <>

}


rov qab retVal;

}


ft_uint32_t Ft_Gpu_Hal_Transfer32 (Ft_Gpu_Hal_Context_t * party, ft_uint32_t tus nqi)

{

ft_uint32_t retVal = 0;

yog hais tias (host-> txheej xwm == FT_GPU_HAL_WRITING) {

Ft_Gpu_Hal_Transfer16 (host, value & 0xFFFF); // LSB ua ntej

Ft_Gpu_Hal_Transfer16 (host, (value >> 16) & 0xFFFF);

} lwm {

retVal = Ft_Gpu_Hal_Transfer16 (party, 0);

retVal | = (ft_uint32_t) Ft_Gpu_Hal_Transfer16 (host, 0) <>

}

rov qab retVal;

}


ft_void_t Ft_Gpu_Hal_EndTransfer (Ft_Gpu_Hal_Context_t * party)

{

#ifdef MSVC_PLATFORM_SPI

/ / cia li disbale CS - xa 0 bytes nrog CS lov tes taw

SPI_ToggleCS ((FT_HANDLE) host-> hal_handle, CAUM);

#endif

#ifdef ARDUINO_PLATFORM_SPI

digitalWrite (FT_ARDUINO_PRO_SPI_CS, HIGH);

#endif

#ifdef MSVC_FT800EMU

Ft_GpuEmu_SPII2C_csHigh ();

#endif

host-> status = FT_GPU_HAL_OPENED;

}


ft_uint8_t Ft_Gpu_Hal_Rd8 (Ft_Gpu_Hal_Context_t * party, ft_uint32_t addr)

{

ft_uint8_t tus nqi;

Ft_Gpu_Hal_StartTransfer (host, FT_GPU_READ, addr);

nqi = Ft_Gpu_Hal_Transfer8 (party, 0);

Ft_Gpu_Hal_EndTransfer (tus tswv tsev);

rov qab tus nqi;

}

ft_uint16_t Ft_Gpu_Hal_Rd16 (Ft_Gpu_Hal_Context_t * party, ft_uint32_t addr)

{

ft_uint16_t tus nqi;

Ft_Gpu_Hal_StartTransfer (host, FT_GPU_READ, addr);

nqi = Ft_Gpu_Hal_Transfer16 (party, 0);

Ft_Gpu_Hal_EndTransfer (tus tswv tsev);

rov qab tus nqi;

}

ft_uint32_t Ft_Gpu_Hal_Rd32 (Ft_Gpu_Hal_Context_t * party, ft_uint32_t addr)

{

ft_uint32_t tus nqi;

Ft_Gpu_Hal_StartTransfer (host, FT_GPU_READ, addr);

nqi = Ft_Gpu_Hal_Transfer32 (party, 0);

Ft_Gpu_Hal_EndTransfer (tus tswv tsev);

rov qab tus nqi;

}

ft_void_t Ft_Gpu_Hal_Wr8 (Ft_Gpu_Hal_Context_t * host, ft_uint32_t addr, ft_uint8_t v)

{

Ft_Gpu_Hal_StartTransfer (host, FT_GPU_WRITE, addr);

Ft_Gpu_Hal_Transfer8 (party, v);

Ft_Gpu_Hal_EndTransfer (tus tswv tsev);

}

ft_void_t Ft_Gpu_Hal_Wr16 (Ft_Gpu_Hal_Context_t * host, ft_uint32_t addr, ft_uint16_t v)

{

Ft_Gpu_Hal_StartTransfer (host, FT_GPU_WRITE, addr);

Ft_Gpu_Hal_Transfer16 (party, v);

Ft_Gpu_Hal_EndTransfer (tus tswv tsev);

}

ft_void_t Ft_Gpu_Hal_Wr32 (Ft_Gpu_Hal_Context_t * host, ft_uint32_t addr, ft_uint32_t v)

{

Ft_Gpu_Hal_StartTransfer (host, FT_GPU_WRITE, addr);

Ft_Gpu_Hal_Transfer32 (party, v);

Ft_Gpu_Hal_EndTransfer (tus tswv tsev);

}



ft_void_t Ft_Gpu_HostCommand (Ft_Gpu_Hal_Context_t * party, ft_uint8_t cmd)

{

#ifdef MSVC_PLATFORM_SPI

ft_uint8_t Transfer_Array [3];

ft_uint32_t DimTransfered;


Transfer_Array [0] = cmd;

Transfer_Array [1] = 0;

Transfer_Array [2] = 0;


SPI_Write (host-> hal_handle, Transfer_Array, sizeof (Transfer_Array), & SizeTransfered, SPI_TRANSFER_OPTIONS_SIZE_IN_BYTES | SPI_TRANSFER_OPTIONS_CHIPSELECT_ENABLE | SPI_TRANSFER_OPTIONS_CHIPSELECT_DISABLE);

#endif

#ifdef ARDUINO_PLATFORM_SPI

digitalWrite (FT_ARDUINO_PRO_SPI_CS, LOW);

SPI.transfer (cmd);

SPI.transfer (0);

SPI.transfer (0);

digitalWrite (FT_ARDUINO_PRO_SPI_CS, HIGH);

#endif

#ifdef MSVC_FT800EMU

// Tsis siv rau hauv FT800EMU

#endif

}


ft_void_t Ft_Gpu_ClockSelect (Ft_Gpu_Hal_Context_t * host, FT_GPU_PLL_SOURCE_T pllsource)

{

Ft_Gpu_HostCommand (host, pllsource);

}

ft_void_t Ft_Gpu_PLL_FreqSelect (Ft_Gpu_Hal_Context_t * host, FT_GPU_PLL_FREQ_T freq)

{

Ft_Gpu_HostCommand (host, freq);

}

ft_void_t Ft_Gpu_PowerModeSwitch (Ft_Gpu_Hal_Context_t * host, FT_GPU_POWER_MODE_T pwrmode)

{

Ft_Gpu_HostCommand (host, pwrmode);

}

ft_void_t Ft_Gpu_CoreReset (Ft_Gpu_Hal_Context_t * party)

{

Ft_Gpu_HostCommand (host, 0x68);

}


ft_void_t Ft_Gpu_Hal_Updatecmdfifo (Ft_Gpu_Hal_Context_t * host, ft_uint16_t suav)

{

host-> ft_cmd_fifo_wp = (host-> ft_cmd_fifo_wp + suav) & 4095;


// 4 bytes mus ua ke

host-> ft_cmd_fifo_wp = (host-> ft_cmd_fifo_wp + 3) & 0xffc;

Ft_Gpu_Hal_Wr16 (host, REG_CMD_WRITE, host-> ft_cmd_fifo_wp);

}


ft_uint16_t Ft_Gpu_Cmdfifo_Freespace (Ft_Gpu_Hal_Context_t * party)

{

ft_uint16_t fullness, retval;


fullness = (host-> ft_cmd_fifo_wp - Ft_Gpu_Hal_Rd16 (party, REG_CMD_READ)) & 4095;

retval = (FT_CMD_FIFO_SIZE - 4) - fullness;

rov qab (tus menyuam yaus);

}

ft_void_t Ft_Gpu_Hal_WrCmdBuf (Ft_Gpu_Hal_Context_t * host, ft_uint8_t * tsis, ft_uint16_t suav)

{

ft_uint32_t ntev = 0, SizeTransfered = 0;

#define MAX_CMD_FIFO_TRANSFER Ft_Gpu_Cmdfifo_Freespace (party)

ua {

ntev = suav;

yog hais tias (ntev> MAX_CMD_FIFO_TRANSFER) {

ntev = MAX_CMD_FIFO_TRANSFER;

}

Ft_Gpu_Hal_CheckCmdBuffer (tus tswv tsev, ntev);


Ft_Gpu_Hal_StartCmdTransfer (host, FT_GPU_WRITE, ntev);

#if txhais (ARDUINO_PLATFORM_SPI) || txhais (MSVC_FT800EMU)

SizeTransfered = 0;

thaum (ntev--) {

Ft_Gpu_Hal_Transfer8 (tus tswv tsev, * tsis tuaj);

tsis ++;

SizeTransfered ++;

}

ntev = Qhov loj me me;

#endif


#ifdef MSVC_PLATFORM_SPI

{

SPI_Write (host-> hal_handle, buffer, ntev, & SizeTransfered, SPI_TRANSFER_OPTIONS_SIZE_IN_BYTES);

ntev = Qhov loj me me;

buffer + = SizeTransfered;

}

#endif

Ft_Gpu_Hal_EndTransfer (tus tswv tsev);

Ft_Gpu_Hal_Updatecmdfifo (tus tswv tsev, ntev);


Ft_Gpu_Hal_WaitCmdfifo_empty (party);


suav - = qhov ntev;

} thaum (suav> 0);

}

#ifdef ARDUINO_PLATFORM_SPI

ft_void_t Ft_Gpu_Hal_WrCmdBufFromFlash (Ft_Gpu_Hal_Context_t * host, FT_PROGMEM ft_prog_uchar8_t * tsis, ft_uint16_t suav)

{

ft_uint32_t ntev = 0, SizeTransfered = 0;

#define MAX_CMD_FIFO_TRANSFER Ft_Gpu_Cmdfifo_Freespace (party)

ua {

ntev = suav;

yog hais tias (ntev> MAX_CMD_FIFO_TRANSFER) {

ntev = MAX_CMD_FIFO_TRANSFER;

}

Ft_Gpu_Hal_CheckCmdBuffer (tus tswv tsev, ntev);


Ft_Gpu_Hal_StartCmdTransfer (host, FT_GPU_WRITE, ntev);



SizeTransfered = 0;

thaum (ntev--) {

Ft_Gpu_Hal_Transfer8 (host, ft_pgm_read_byte_near (tsis tuaj));

tsis ++;

SizeTransfered ++;

}

ntev = Qhov loj me me;


Ft_Gpu_Hal_EndTransfer (tus tswv tsev);

Ft_Gpu_Hal_Updatecmdfifo (tus tswv tsev, ntev);


Ft_Gpu_Hal_WaitCmdfifo_empty (party);


suav - = qhov ntev;

} thaum (suav> 0);

}

#endif

ft_void_t Ft_Gpu_Hal_CheckCmdBuffer (Ft_Gpu_Hal_Context_t * host, ft_uint16_t suav)

{

ft_uint16_t getfreespace;

ua {

getfreespace = Ft_Gpu_Cmdfifo_Freespace (party);

} thaum (getfreespace <>

}

ft_void_t Ft_Gpu_Hal_WaitCmdfifo_empty (Ft_Gpu_Hal_Context_t * party)

{

thaum (Ft_Gpu_Hal_Rd16 (party, REG_CMD_READ)! = Ft_Gpu_Hal_Rd16 (party, REG_CMD_WRITE));

host-> ft_cmd_fifo_wp = Ft_Gpu_Hal_Rd16 (host, REG_CMD_WRITE);

}

ft_void_t Ft_Gpu_Hal_WrCmdBuf_nowait (Ft_Gpu_Hal_Context_t * host, ft_uint8_t * tsis, ft_uint16_t suav)

{

ft_uint32_t ntev = 0, SizeTransfered = 0;

#define MAX_CMD_FIFO_TRANSFER Ft_Gpu_Cmdfifo_Freespace (party)

ua {

ntev = suav;

yog hais tias (ntev> MAX_CMD_FIFO_TRANSFER) {

ntev = MAX_CMD_FIFO_TRANSFER;

}

Ft_Gpu_Hal_CheckCmdBuffer (tus tswv tsev, ntev);


Ft_Gpu_Hal_StartCmdTransfer (host, FT_GPU_WRITE, ntev);


// # ifdef ARDUINO_PLATFORM_SPI

#if txhais (ARDUINO_PLATFORM_SPI) || txhais (MSVC_FT800EMU)

SizeTransfered = 0;

thaum (ntev--) {

Ft_Gpu_Hal_Transfer8 (tus tswv tsev, * tsis tuaj);

tsis ++;

SizeTransfered ++;

}

ntev = Qhov loj me me;

#endif

#ifdef MSVC_PLATFORM_SPI

{

SPI_Write (host-> hal_handle, buffer, ntev, & SizeTransfered, SPI_TRANSFER_OPTIONS_SIZE_IN_BYTES);

ntev = Qhov loj me me;

buffer + = SizeTransfered;

}

#endif


Ft_Gpu_Hal_EndTransfer (tus tswv tsev);

Ft_Gpu_Hal_Updatecmdfifo (tus tswv tsev, ntev);


// Ft_Gpu_Hal_WaitCmdfifo_empty (party);


suav - = qhov ntev;

} thaum (suav> 0);

}



ft_uint8_t Ft_Gpu_Hal_WaitCmdfifo_empty_status (Ft_Gpu_Hal_Context_t * party)

{

yog tias (Ft_Gpu_Hal_Rd16 (host, REG_CMD_READ)! = Ft_Gpu_Hal_Rd16 (host, REG_CMD_WRITE))

{

rov qab 0;

}

lwm tus

{

host-> ft_cmd_fifo_wp = Ft_Gpu_Hal_Rd16 (host, REG_CMD_WRITE);

rov qab 1;

}

}


ft_void_t Ft_Gpu_Hal_WaitLogo_Finish (Ft_Gpu_Hal_Context_t * party)

{

ft_int16_t cmdrdptr, cmdwrptr;


ua {

cmdrdptr = Ft_Gpu_Hal_Rd16 (host, REG_CMD_READ);

cmdwrptr = Ft_Gpu_Hal_Rd16 (host, REG_CMD_WRITE);

} thaum ((cmdwrptr! = cmdrdptr) || (cmdrdptr! = 0));

host-> ft_cmd_fifo_wp = 0;

}


ft_void_t Ft_Gpu_Hal_ResetCmdFifo (Ft_Gpu_Hal_Context_t * party)

{

host-> ft_cmd_fifo_wp = 0;

}


ft_void_t Ft_Gpu_Hal_WrCmd32 (Ft_Gpu_Hal_Context_t * party, ft_uint32_t cmd)

{

Ft_Gpu_Hal_CheckCmdBuffer (party, sizeof (cmd));

Ft_Gpu_Hal_Wr32 (host, RAM_CMD + host-> ft_cmd_fifo_wp, cmd);

Ft_Gpu_Hal_Updatecmdfifo (party, sizeof (cmd));

}


ft_void_t Ft_Gpu_Hal_ResetDLBuffer (Ft_Gpu_Hal_Context_t * party)

{

host-> ft_dl_buff_wp = 0;

}

/ * Toggle PD_N pin ntawm FT800 pawg thawj coj saib kev siv fais fab * /

ft_void_t Ft_Gpu_Hal_Powercycle (Ft_Gpu_Hal_Context_t * party, ft_bool_t li)

{

yog tias (txog)

{

#ifdef MSVC_PLATFORM

// PDN teev rau 0, txuas xiav hlau ntawm MPSSE rau PDN # ntawm FT800 lub rooj tsavxwm (FT_WriteGPIO (host-> hal_handle, 0xBB, 0x08);

Ft_Gpu_Hal_Sleep (20);


FT_WriteGPIO (host-> hal_handle, 0xBB, 0x88); // PDN teeb rau 1

Ft_Gpu_Hal_Sleep (20);

#endif

#ifdef ARDUINO_PLATFORM

digitalWrite (FT800_PD_N, LOW);

Ft_Gpu_Hal_Sleep (50);


digitalWrite (FT800_PD_N, HIGH);

Ft_Gpu_Hal_Sleep (50);

#endif

} lwm tus

{

#ifdef MSVC_PLATFORM

FT_WriteGPIO (host-> hal_handle, 0xBB, 0x88); // PDN teeb rau 1

Ft_Gpu_Hal_Sleep (20);

// PDN teev rau 0, txuas xiav hlau ntawm MPSSE rau PDN # ntawm FT800 lub rooj tsavxwm (FT_WriteGPIO (host-> hal_handle, 0xBB, 0x08);

Ft_Gpu_Hal_Sleep (20);

#endif

#ifdef ARDUINO_PLATFORM

digitalWrite (FT800_PD_N, HIGH);

Ft_Gpu_Hal_Sleep (20);

digitalWrite (FT800_PD_N, LOW);

Ft_Gpu_Hal_Sleep (20);

#endif

}

}



ft_void_t Ft_Gpu_Hal_WrMemFromFlash (Ft_Gpu_Hal_Context_t * host, ft_uint32_t addr, const ft_prog_uchar8_t * tsis, ft_uint32_t ntev)

{

ft_uint32_t SizeTransfered = 0;


Ft_Gpu_Hal_StartTransfer (host, FT_GPU_WRITE, addr);


#if txhais (ARDUINO_PLATFORM_SPI) || txhais (MSVC_FT800EMU)

thaum (ntev--) {

Ft_Gpu_Hal_Transfer8 (host, ft_pgm_read_byte_near (tsis tuaj));

tsis ++;

}

#endif


#ifdef MSVC_PLATFORM_SPI

{

SPI_Write ((FT_HANDLE) host-> hal_handle, buffer, ntev, & SizeTransfered, SPI_TRANSFER_OPTIONS_SIZE_IN_BYTES);

}

#endif



Ft_Gpu_Hal_EndTransfer (tus tswv tsev);

}


ft_void_t Ft_Gpu_Hal_WrMem (Ft_Gpu_Hal_Context_t * host, ft_uint32_t addr, const ft_uint8_t * tsis, ft_uint32_t ntev)

{

ft_uint32_t SizeTransfered = 0;


Ft_Gpu_Hal_StartTransfer (host, FT_GPU_WRITE, addr);


#if txhais (ARDUINO_PLATFORM_SPI) || txhais (MSVC_FT800EMU)

thaum (ntev--) {

Ft_Gpu_Hal_Transfer8 (tus tswv tsev, * tsis tuaj);

tsis ++;

}

#endif


#ifdef MSVC_PLATFORM_SPI

{

SPI_Write ((FT_HANDLE) host-> hal_handle, buffer, ntev, & SizeTransfered, SPI_TRANSFER_OPTIONS_SIZE_IN_BYTES);

}

#endif



Ft_Gpu_Hal_EndTransfer (tus tswv tsev);

}



ft_void_t Ft_Gpu_Hal_RdMem (Ft_Gpu_Hal_Context_t * host, ft_uint32_t addr, ft_uint8_t * tsis, ft_uint32_t ntev)

{

ft_uint32_t SizeTransfered = 0;


Ft_Gpu_Hal_StartTransfer (host, FT_GPU_READ, addr);


#if txhais (ARDUINO_PLATFORM_SPI) || txhais (MSVC_FT800EMU)

thaum (ntev--) {

* ntas = Ft_Gpu_Hal_Transfer8 (party, 0);

tsis ++;

}

#endif


#ifdef MSVC_PLATFORM_SPI

{

SPI_Read ((FT_HANDLE) party-> hal_handle, buffer, ntev, & SizeTransfered, SPI_TRANSFER_OPTIONS_SIZE_IN_BYTES);

}

#endif


Ft_Gpu_Hal_EndTransfer (tus tswv tsev);

}


ft_int32_t Ft_Gpu_Hal_Dec2Ascii (ft_char8_t * pSrc, ft_int32_t tus nqi)

{

ft_int16_t Ntev;

ft_char8_t * pdst, charval;

ft_int32_t CurrVal = tus nqi, tmpval, kuv;

ft_char8_t tmparray [16], idx = 0;


Ntev = strlen (pSrc);

pdst = pSrc + Ntev;


yog tias (0 == tus nqi)

{

* pdst ++ = '0';

* pdst ++ = '';

rov qab 0;

}


yog tias (CurrVal <>

{

* pdst ++ = '-';

CurrVal = - CurrVal;

}

/ * ntxig rau tus nqi * /

thaum (CurrVal> 0) {

tmpval = CurrVal;

CurrVal / = 10;

tmpval = tmpval - CurrVal * 10;

charval = '0' + tmpval;

tmparray [idx ++] = charval;

}


rau (i = 0; i

{

* pdst ++ = tmparray [idx - i - 1];

}

* pdst ++ = '';


rov qab 0;

}


ft_void_t Ft_Gpu_Hal_Sleep (ft_uint16_t ms)

{

#if txhais (MSVC_PLATFORM) || txhais (MSVC_FT800EMU)

Pw tsaug zog (ms);

#endif

#ifdef ARDUINO_PLATFORM

ncua (ms);

#endif

}